数码营电子:基于微型控制器的编程、电路设计与电子产品制做。邮箱:shumaying@hotmail.com
STM8S001J3
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Key Features
Core
16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
Extended instruction set
Memories
Program memory: 8 Kbytes Flash memory; data retention 20 years at 55 °C after 100 cycles
RAM: 1 Kbyte
Data memory: 128-byte true data EEPROM; endurance up to 100 k write/erase cycles
Clock, reset and supply management
2.95 V to 5.5 V operating voltage
Flexible clock control, 3 master clock sources
External clock input
Internal, user-trimmable 16 MHz RC
Internal low-power 128 kHz RC
Clock security system with clock monitor
Power management
Low-power modes (wait, active-halt, halt)
Switch-off peripheral clocks individually
Permanently active, low-consumption power-on and power-down reset
Interrupt management
Nested interrupt controller with 32 interrupts
Up to 5 external interrupts
Timers
Advanced control timer: 16-bit, 2 CAPCOM channels, 2 outputs, dead-time insertion and flexible synchronization
16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)
8-bit basic timer with 8-bit prescaler
Auto wakeup timer
Window and independent watchdog timers
Communications interfaces
UART, SmartCard, IrDA, LIN master mode
SPI unidirectional interface up to 8 Mbit/s (master simplex mode, slave receiver only)
I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit ADC, ± 1 LSB ADC with up to 3 multiplexed channels, scan mode and analog watchdog
Internal reference voltage measurement
I/Os
Up to 5 I/Os including 4 high-sink outputs
Highly robust I/O design, immune against current injection
Development support
Embedded single-wire interface module (SWIM) or fast on-chip programming and non-intrusive debugging
Vocabulary:
- dead-time - na.停滞期 Web死区时间;空载时间;停滞时间
- immune
US [ɪ'mjun] UK [ɪ'mjuːn]
adj.有免疫力;不受影响;受保护;免除 n.免疫者 Web免疫的;免除的;不受影响的
- intrusive
US [ɪn'trusɪv] UK [ɪn'truːsɪv]
adj.侵入的;闯入的;侵扰的;烦扰的 Web侵入性;侵入式;打扰的
